The present disclosure relates to semiconductor memory devices, and more particularly, to semiconductor memory devices having negative boost word line drivers for causing the levels of word lines to have a negative voltage when the device is reset.
In recent years, for embedded dynamic random access memory (DRAM), there has been particularly a demand for higher integration which allows system-on-chip (SOC) with low cost. The area of a memory device is dominated by a memory array. Therefore, in order to achieve higher integration, attempts have been made to reduce the area of each memory cell by applying microfabrication techniques to memory cell transistors, or memory cell capacitors using high-k insulating film.
In DRAM, in order to fully restore a voltage having a bit line amplitude in a memory cell capacitor, a transistor having a thick film is used as the memory cell transistor because a voltage higher than the threshold voltage (Vth) needs to be applied to the gate. At the same time, the memory cell transistor needs to have a low leakage characteristic in order to hold data of the memory cell capacitor. Therefore, the threshold voltage of the memory cell transistor is set to a high value, and the back bias effect is large, and therefore, the set level of word lines is a voltage which is higher, by 1 V or more, than the high voltage of bit lines.
On the other hand, the gate length of the memory cell transistor needs to be decreased in order to reduce the size of the memory cell transistor. Also, the thickness of the memory cell transistor needs to be decreased in order to reduce a leakage current which is caused by the short channel effect. In this case, a voltage at the word line set level needs to be decreased in terms of reliability, and at the same time, the threshold voltage Vth needs to be decreased in order to ensure the restoration level of the memory cell capacitor, and the leakage current needs to be prevented from increasing.
To solve the above problems, an architecture called a negative boost word line scheme is known. In this technique, satisfactory characteristics required for the memory cell transistor may be obtained by modifying the reset level of word lines from a ground voltage to a negative boost voltage level.
When the negative boost word line scheme is introduced, a word line driver which can shift the level of a signal having a bit line voltage amplitude in both the positive direction and the negative direction is additionally required. As examples of such a negative boost word line driver, various level shift circuits are proposed in Japanese Patent Publication No. H07-307091.
Japanese Patent Publication No. H08-63964 describes a configuration in which an address decoding function is provided, and a level shift voltage in both the positive direction and the negative direction can be applied to a word line using a small number of elements. An example of this conventional word line driver is shown in FIG. 7. In FIG. 7, reference characters 100a and 100b indicate word line drivers, reference characters XA, XB, WD<0>, and WD<1> indicate word line select address signals, a reference character /STWD indicates a word line reset control signal, reference characters WL<0> and WL<1> indicate word lines, a reference character BL indicates a bit line, reference characters /AD and Node1 indicate internal nodes, a reference character Vdd indicates the high voltage of the bit line, a reference character Vss indicates the low voltage of the bit line, a reference character Vpp indicates the set level voltage of the word lines, a reference character Vw indicates the reset level voltage of the word lines, a reference character Vcp indicates the plate voltage of a memory cell, reference characters QN1, QN2, QAN1, and QAN2 indicate NMOS transistors, reference characters QP1-QP3, QAP1, and QAP2 indicate PMOS transistors, a reference character QC indicates a memory cell transistor, and a reference character C indicates a memory cell capacitor.
Operation of the word line driver 100a thus configured will be described with reference to a timing diagram shown in FIG. 8. Initially, in a reset state before timing t10, the word line reset control signal /STWD is low, so that the level of the internal node Node1 is Vpp, and the word line WL<0> is at the reset level Vw. The word line WL<1> driven by the adjacent word line driver 100b is similarly held at the reset level Vw (not shown). Thereafter, at timing t10, a portion of an address input to the word line driver 100a is selected (logic high), and the internal node /AD goes low. At timing t11, WD<0> which is a superimposition of a word line activate signal and an address signal goes high, and at the same time, the word line reset control signal /STWD goes high, so that the level of the internal node Node1 goes low, and the word line WL<0> goes to the set level Vpp. Because WD<1> is low (non-selected state), the adjacent word line driver 100b remains in the reset state although the internal node /AD connected commonly to the word line drivers 100a and 100b is low. Thereafter, at timing t12, WD<0> goes low, and the word line reset control signal /STWD goes low, so that the internal node Node1 goes high, and the voltage of the word line WL<0> returns to the reset level Vw. Thereafter, at timing t13, the word line select address signals XA and XB and the internal node /AD return to their original states. Here, t10 and t11, or t12 and t13, may be the same timing.
In the above configuration, |Vw| is applied between the gate and source of the NMOS transistor QN1 when the word line WL<0> is selected, and therefore, a leakage current is likely to flow from the power supply Vpp to the power supply Vw. Therefore, the threshold voltage of the NMOS transistor QN1 is set to be higher than those of transistors around the transistor QN1. In the case of embedded DRAM, the transistor QN1 is typically formed using the same gate oxide film of a high-voltage transistor of a logic circuit or the memory cell transistor QC, whereby the number of processes is decreased to reduce the cost. However, in the case of the configuration including the negative boost word line driver, for example, when the memory device is reset, the source-to-drain voltage of the PMOS transistor QP1, the gate-to-source voltage of the NMOS transistor QN1, and the gate-to-source voltage of the PMOS transistor QP2 are all Vpp+|Vw| (> Vpp), and therefore, the reliability is likely to be degraded due to voltage stress.
To solve this problem, there is, for example, a known technique of reducing the voltage stress by inserting a diode transistor, as described in, for example, Japanese Patent Publication Nos. 2001-297583 and H11-283369.
Moreover, the negative boost word line driver may suffer from an increase in power consumption and current noise of the negative boost power supply. Because the negative boost voltage is generated using a charge pump having low power supply efficiency, power consumption is likely to increase if a discharged current from a word line increases. In addition, it takes a long time to cause a changed voltage level to return to the set level. As a result, the word line reset level changes, so that the leakage current of the memory cell transistor increases, and therefore, the charge holding characteristic is degraded.
To solve this problem, there is, for example, a known technique of, when a word line is reset, temporarily discharging the word line to a ground voltage, and thereafter, discharging the word line to the negative boost power supply, thereby reducing the discharged current to the negative boost power supply to reduce power consumption and improve voltage stability, as described in, for example, Japanese Patent Publication Nos. H10-241361 and 2002-352580.